1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly, to a semiconductor memory devices including an output buffer circuit which outputs a signal corresponding to storage data.
2. Description of the Background Art
As semiconductor memory devices capable of operating at higher speeds have been developed, there is a need to increase the driving capability of an output buffer circuit in such a semiconductor memory device.
FIG. 14 is a circuit diagram of a first example of the basic configuration of an output buffer circuit for use in a conventional semiconductor memory device.
The output buffer circuit shown in FIG. 14 includes an output terminal OUT, a level changing circuit 220 which receives a first internal control signal HOUT generated based on storage data to output, and changes its "H" level from the level of an internal lowered potential Vcc lowered from an external power supply potential Vdd to the level of an internal boosted potential Vpp produced in the semiconductor device, inverters 216 and 218 connected in series to receive the output of level changing circuit 220, an N channel MOS transistor 210 coupled between external power supply potential Vdd and output terminal OUT to receive the output of inverter 218 at its gate, and an N channel MOS transistor 212 coupled between output terminal OUT and a ground potential Vss to receive a second internal control signal LOUT generated based on storage data to output at its gate.
Level changing circuit 220 includes an N channel MOS transistor 206 which receives first internal control signal HOUT at its gate, an inverter 214 which receives and inverts first internal control signal HOUT, and an N channel MOS transistor 208 which receives the output of inverter 214 at its gate.
The sources of N channel MOS transistors 206 and 208 are both coupled to ground potential Vss.
Level changing circuit 220 further includes a P channel MOS transistor 202 coupled between internal boosted potential Vpp and the drain of N channel MOS transistor 206 to receive the potential of the drain of N channel MOS transistor 208 at its gate, and a P channel MOS transistor 204 coupled between internal boosted potential Vpp and the drain of N channel MOS transistor 208 to receive the potential of the drain of N channel MOS transistor 206 at its gate.
Level changing circuit 220 outputs, to inverter 216, an output signal from a node N102 to which the drain of N channel MOS transistor 208 is connected, in other words, outputs a signal which is in phase with first internal control signal HOUT and attains the level of internal boosted potential Vpp at its "H" level.
The configurations of N channel MOS transistors 210 and 212 serving as output transistors in the conventional output buffer circuit shown in FIG. 14 will be now described.
FIG. 15 is a diagram for use in illustration of cross sections of output transistors 210 and 212 in the conventional output buffer circuit in FIG. 14.
Referring to FIG. 15, a first P well region 266 and a second P well region 268 are formed on a main surface of a P type silicon substrate 270 in the conventional semiconductor memory device, and N channel MOS transistors 212 and 210 are formed in the first and second P well regions 266 and 268, respectively.
N channel MOS transistor 212 includes N type impurity regions, i.e., a source 252 and a drain 256 and a gate electrode 254. N channel MOS transistor 210 includes N type impurity regions, i.e., a source 258 and a drain 262 and a gate electrode 260.
In the Dynamic Random Access Memory (hereinafter simply referred to as "DRAM"), the P type silicon substrate is normally provided with a potential lower than a ground potential. In FIG. 15, a P type impurity region 264 is formed on the main surface of P type silicon substrate 270, and P type silicon substrate 270 is provided with a negative potential Vbb through P type impurity region 264.
It is quite significant in the DRAM to thus provide a negative voltage to the P type silicon substrate in order to prevent charges from coming into the substrate at the time of the undershoot of an input signal, thereby to prevent data destruction of data in a memory cell, and to reduce a PN junction capacitance to be the floating capacitance of a bit line for the purpose of increasing the operation speed of the circuit.
FIG. 16 is an operation waveform chart for use in illustration of the operation of the output buffer circuit shown in FIG. 14.
Referring to FIGS. 14 and 16, let us now assume that second internal control signal LOUT is in an "L" state, wherein N channel MOS transistor 212 is in a non-conductive state.
If the level of output terminal OUT is initially 0V, first internal control signal HOUT is at an "L" level at time t1, and N channel MOS transistor 206 is in a non-conductive state.
Inverter 214 applies the inverse of first internal control signal HOUT to the gate of N channel MOS transistor 208, which then attains a conductive state, and node N102 attains an "L" level.
P channel MOS transistor 202, upon receiving the potential of node N102 at its gate, conducts and applies boosted potential Vpp to the gate of P channel MOS transistor 204. As a result, P channel MOS transistor 204 attains a non-conductive state, and the potential of node N102, in other words the level of the output of the level changing circuit is determined at an "L" level. As a result, the gate potential VG of N channel MOS transistor 210 attains an "L" level by the function of the series-connection of inverters 216 and 218.
As first internal control signal HOUT rises from 0V to internal lowered potential Vcc at time t2, N channel MOS transistor 206 conducts accordingly, while first internal control signal HOUT is inverted by inverter 214, and N channel MOS transistor 208 receiving the inverse at its gate attains a non-conductive state. Therefore, an "L level is applied to the gate of P channel MOS transistor 204 through N channel MOS transistor 206 which turns on P channel MOS transistor 204, and the potential of node N102 is raised to internal boosted potential Vpp.
P channel MOS transistor 202 attains a non-conductive state, because its gate potential, in other words, the potential of node N102 attains an "H" level. As a result, the output of level changing circuit 220, in other words the potential of node N102 is determined at the level of internal boosted potential Vpp, and the "H" level of first internal control signal HOUT is changed from the level of internal lowered potential Vcc to the level of internal boosted potential Vpp. The potential is transmitted through inverters 216 and 218, which raises the gate potential VG of N channel MOS transistor 210 from 0V to internal boosted potential Vpp. N channel MOS transistor 210 conducts accordingly, and starts raising the potential of output terminal OUT.
At time t3, a load capacitance connected with output terminal OUT outside the semiconductor memory device is sufficiently charged, and the potential of output terminal OUT is stabilized.
Herein, the current from the semiconductor memory device which charges the externally connected load capacitance through output terminal OUT is supplied by N channel MOS transistor 210 and given by the following expression: EQU IDS=K'(Vgs-Vth).sup.2 (1)
wherein Vgs is a gate-source potential difference, Vth a threshold voltage, and K' a constant. The current supplied outside the semiconductor memory device from output terminal OUT is affected by the threshold voltage Vth of N channel MOS transistor 210, and the larger Vth, the smaller supplied current IDS.
At time t3, however, the threshold voltage Vth of N channel MOS transistor 210 increases by a substrate biasing effect, which will be now described.
At time t3, the source potential of N channel MOS transistor 210 is Vout, the potential of output terminal OUT, while the substrate portion of N channel MOS transistor 210 is at negative potential Vbb as described above, and therefore the source-substrate potential difference Vsb of N channel MOS transistor 210 is extremely large at time t3.
In general, the larger the source-substrate potential difference Vsb of a MOS transistor, the larger the threshold voltage Vth of the MOS transistor by a substrate biasing effect. Therefore, the Vth of N channel MOS transistor 210 increases at time t3 at which source-substrate potential difference Vsb is large.
Herein, based on expression (1), if threshold voltage Vth is large, output current IDS may be increased by increasing the gate-source potential difference Vgs of the MOS transistor by the corresponding amount. According to a conventional technique, a large output current is secured for output terminal OUT by setting the gate potential VG of N channel MOS transistor 210 at a sufficiently high level in other words setting boosted potential Vpp at a sufficiently high level, when output terminal OUT outputs an "H" level.
In recent years, however, as further high density integration of semiconductor devices and associated down sizing of MOS transistors have proceeded, the thickness of a gate oxide film in such a MOS transistor tends to be reduced every year accordingly. As a result, the breakdown voltage of a gate oxide film is lowered, and the reliability of a MOS transistor may be affected by setting the gate voltage at a high level. Consequently, raising boosted potential Vpp to a high level is most unlikely in the future.
Internal boosted potential Vpp is generated by a charge pump circuit in the semiconductor memory device based on external power supply potential Vdd.
The charge pump circuit produces a high potential by pumping up charges to the internal boosted voltage node at a prescribed frequency, using a capacitor formed on the semiconductor device.
If current consumption by internal boosted potential Vpp increases, the capacitance of the capacitor should be increased, or the prescribed frequency should be set higher. Thus increasing the capacitance of the capacitor requires a large area on the semiconductor substrate, which gives rise to increase in the cost of the semiconductor memory device. Meanwhile, the prescribed frequency may be increased to only a limited level, and the efficiency of transferring charges is lowered.
Japanese Patent Laying-Open No. 9-139077 proposes a pre-boost circuit which provides a load with current both from an external power supply and an internal boosted voltage node.
FIG. 17 is a circuit diagram showing the configuration of the pre-boost circuit. Referring to FIG. 17, an N channel MOS transistor QN1 is coupled between an external power supply potential Vdd and a node OUT1, and provided with an internal control signal IN1 at its gate. A P channel MOS transistor QN2 is coupled between internal boosted potential Vpp and node OUT1, and provided with an internal control signal IN2 at its gate, and the substrate portion is coupled to internal boosted potential Vpp.
When node OUT1 is boosted to the level of internal boosted potential Vpp, the circuit first turns on N channel MOS transistor QN1, previously boosts node OUT1 to the level of external power supply potential Vdd, and then turns on P channel MOS transistor QN2 to reduce current passed from internal boosted potential Vpp to node OUT1, in order to restrict current consumption with internal boosted potential Vpp.
In the circuit as shown in FIG. 17, however, when the level of boosted potential Vpp is instable, particularly at the time of turning on the power supply to use a DRAM, for example, the operation may be instable. Such a state will be further described.
FIG. 18 is a cross sectional view of the configuration of the pre-boost circuit in FIG. 17 used in a DRAM.
Referring to FIG. 18, an N well region 366 and a P well region 368 are formed on a P type silicon substrate 370, a P channel MOS transistor QN2 is formed in N well region 366 and an N channel MOS transistor QN1 is formed in P well region 368.
P type silicon substrate 370 is supplied with a negative potential Vbb through a P type impurity region 364, and N well region 366 is supplied with an internal boosted potential Vpp through an N type impurity region 372. A P type impurity region 352, the source of P channel MOS transistor QN2 is coupled with internal boosted potential Vpp, and a P type impurity region 356, the drain of P channel MOS transistor QN2 and an N type impurity region 358, the source of N channel MOS transistor QN1 are connected together to node OUT1.
A gate electrode 354, the gate of P channel MOS transistor QN2 is provided with internal control signal IN2 as an input, and a gate electrode 360, the gate of N channel MOS transistor QN1 is provided with internal control signal IN1 as an input.
Herein, immediately after turning on the power supply of the semiconductor memory device, or a terminal is affected by a disturbance, the charge pump circuit generating internal boosted potential Vpp becomes instable, which may cause internal boosted potential Vpp to be lower than external power supply potential Vdd.
In such a case, if internal control signal IN1 can turn on N channel MOS transistor QN1, node OUT1 is pulled to the level of external power supply potential Vdd, and a forward biasing is imposed on the PN junction between P type impurity region 356 and N well region 366. Then, a parasitic PNP type bipolar transistor formed of P type impurity region 356, N well region 366 and P type silicon substrate 370 is turned on, which could pass current from P type impurity region 356 to P type silicon substrate 370. Such a state could lead to a loss of data in a memory cell in the DRAM, and to a latch up.
Thus, if the potential of a well is pulled to the level of a potential generated in the semiconductor device, countermeasure should be provided in the circuit configuration to cope with an unpredictable undesirable situation as described above.